Course on STA and Timing Constraints
Learn each and everything about STA and timing constraints
Updated on Oct, 2025
Language - English
Teaching and Academics ,Engineering,Electrical Engineering
Lectures -26
Duration -2.5 hours
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Course Description
This course all basic concepts in Static Timing Analysis and Timing Constraints
- Introduction to Static Timing Analysis
- Timing Paths
- Startpoint, Endpoint, Combinational Logic
- Setup and Hold Check Definition
- Understanding details of setup slack calculation
- Multiple types of Timing Paths
- Design Rule Checks
- Timing checks on Async Pins
- Clock Gating Checks
- Timing Latches
- STA in presence of Multiple Clocks
- Timing Arcs
- Cell Delays and Models
- Impact of clock network on STA
- Understanding Text Report in STA
- Overview of SDC
- Clock and Generated Clock Definitions
- Clock Groups
- Clock Characteristics Specification
- Port Delays
- Timing Exceptions
- Other SDC commands
Goals
Learn all the basics of STA and timing constraints
Prerequisites
Basics of logic and digital design
Curriculum
Check out the detailed breakdown of what’s inside the course
Introduction
1 Lectures
-
Introduction
00:30
00:30
STA Definition
1 Lectures
Timing paths
1 Lectures
Timing path elements
1 Lectures
Setup and hold checks
1 Lectures
Slack calculation
1 Lectures
Other timing checks
1 Lectures
Design rule checks
1 Lectures
Checks on async pins
1 Lectures
Clock gating checks
1 Lectures
Latch timing
1 Lectures
Multiple clocks
1 Lectures
Timing arc and timing sense
1 Lectures
Cell delays and clock network
1 Lectures
Setup and hold detailed
1 Lectures
STA text report
1 Lectures
Crosstalk and noise
1 Lectures
Operating modes and other variations
1 Lectures
SDC overview
1 Lectures
Clocks
1 Lectures
Generated clocks
1 Lectures
Clock groups
1 Lectures
Clock properties
1 Lectures
Boundary constraints
1 Lectures
Timing exceptions
1 Lectures
Multiple modes
1 Lectures
Instructor Details
Vikas Sachdeva
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